FIG. 1 is an illustration of a conventional four transistor (4T) pixel 100. The pixel 100 includes a light sensitive element 101, shown as a photodiode, a floating diffusion node C, and four transistors: a transfer transistor 111, a reset transistor 112, a source follower transistor 113, and a row select transistor 114. The pixel 100 accepts a TX control signal for controlling the conductivity of the transfer transistor 111, a RST control signal for controlling the conductivity of the reset transistor 112, and a ROW select signal for controlling the conductivity of the row select transistor 114. The voltage at the floating diffusion node C controls the conductivity of the source follower transistor 113. The output of the source follow transistor 113 is presented at node B when the row select transistor 114 is conducting.
The states of the transfer and reset transistors 111, 112 determine whether the floating diffusion node C is coupled to the light sensitive element 101 for receiving a photo-generated charge generated by the light sensitive element 101 following a charge integration period, or a source of pixel power VAAPIX from node A during a reset period.
The pixel 100 is operated as follows. The ROW control signal is asserted high to cause the row select transistor 114 to conduct. At the same time, the RST control signal is asserted high while the TX control signal is asserted low. This couples the floating diffusion node C to the pixel power VAAPIX at node A, and resets the voltage at node C to the pixel power VAAPIX. The pixel 100 outputs a reset signal Vrst at node B. As will be explained in greater detail below in connection with FIG. 2, node B is typically coupled to a column line 215 (FIG. 2) of an imager 200.
After the reset signal Vrst has been output, the RST control signal is asserted low. The light sensitive element 101 is exposed to incident light and accumulates charge based on the level of the incident light during a charge integration period. After the charge integration period, the TX control signal is asserted. This couples the floating diffusion node C to the light sensitive element 101. Charge flows through the transfer transistor 111 and diminishes the voltage at the floating diffusion node C. The pixel 100 outputs a photo signal Vsig at node B. The reset and photo signals Vrst, Vsig are different components of the overall pixel output (i.e., Voutput=Vrst−Vsig), which is typically processed by an imager 200 (FIG. 2) as explained in greater detail below.
FIG. 2 is an illustration of an imager 200 that includes a plurality of pixels 100 forming a pixel array 201. Due to space limitations the pixel array 201 is drawn as a 4 row by 4 column array. One skilled in the art would recognize that in most imagers 200 the pixel array 201 would ordinarily include many more rows and columns, and thus, many more pixels 100.
The imager 200 also includes row circuitry 210, column circuitry 220, a digital conversion circuit 230, a digital processing circuit 240, and a storage device 250. The imager 200 also includes a controller 260. The row circuitry 210 selects a row of pixels 100 from the pixel array 201. The pixels 100 in the selected row output, at different times, their reset and pixel signals Vrst, Vsig to the column circuitry 220, via column lines 215. The column circuit 220 samples and holds the reset and pixel signals Vrst, Vsig. The column circuitry 220 also forms an analog pixel output signal Vpixel from the difference Vrst−Vsig, and outputs the Vpixel signal on lines 216 to the digital conversion circuit 230.
Now referring to FIG. 3, it can be seen that the column circuitry 220 comprises a plurality of analog pixel processing circuits 221 and a plurality of corresponding load circuits 310. Each column line 215 is coupled, in parallel at node D, to a respective analog processing circuit 221 and a respective load circuit 310. Each analog pixel processing circuit 221 accepts the reset and pixel signals Vrst, Vsig output from a pixel at different times on column line 215, and forms an analog pixel signal Vpixel as the difference between the reset and pixel signals Vrst, Vsig (i.e., Vpixel=Vrst−Vsig). The signal Vpixel is output on line 216.
FIG. 4 is a more detailed illustration of a single analog pixel processing circuit 221, its associated column and output lines 215, 216 and load circuit 310. The analog pixel processing circuit 221 includes a first signal path SP1 for sampling and holding a reset signal Vrst and a second signal path SP2 for sampling and holding a photo signal Vsig. The sampled and held Vrst, Vsig signals are provided to a gain stage 450, which outputs the pixel signal Vpixel on line 216. Additionally, the analog processing circuit 221 further includes switches 431, 432, and 433.
The first signal path SP1 includes switch 421, capacitor 441, and switch 434. The state of switch 421 is controlled by the sample and hold reset (SHR) control signal, which is asserted high when a pixel is outputting the reset signal Vrst on line 215. The SHR control signal is asserted low if the pixel is not outputting a reset signal Vrst.
The second signal path SP2 includes switch 422, capacitor 442, and switch 435. The state of switch 421 is controlled by the sample and hold signal (SHS) control signal, which is asserted high when a pixel is outputting the photo signal Vsig on line 215. The SHS control signal is asserted low if the pixel is not outputting a photo signal Vsig.
The circuit 221 operates as follows. First, before a pixel coupled to line 215 outputs either the reset or photo signals Vrst, Vsig, the capacitors 441, 442 must be set to a known state. Thus, switches 421, 422, 432, 433, 434, and 435 are each opened, while switch 431 is closed. This equalizes the charges on the sides of capacitors 441, 442 closest to node D. Switches 432, 433 are then closed, to couple the sides of capacitors 441, 442, closest to gain stage 450 to a clamp voltage Vcl. Switches 431, 432, 433 are then opened.
The pixel coupled to output line 215 then outputs a reset signal Vrst on line 215. The SHR control signal is asserted high while the SHS control signal is asserted low. This combination of the states of the SHR and SHS control signals causes switch 421 to close while maintaining switch 422 in an open state, thereby coupling only the first signal path SP1 to node D. The reset signal Vrst output by the pixel causes the charge level of capacitor 441 to change. Once the pixel has completed outputting the reset signal Vrst, the SHR control signal is asserted low, causing switch 421 to open, thereby decoupling the capacitor 441 from node D.
The pixel coupled to output line 215 then outputs a photo signal Vsig on line 215. The SHS control signal is asserted high while the SHR control signal is asserted low. This combination of the states of the SHR and SHS control signals causes switch 422 to close while maintaining switch 421 in an open state, thereby coupling only the second signal path SP2 to node D. The photo signal Vsig output by the pixel causes the charge level of capacitor 442 to change. Once the pixel has completed outputting the photo signal Vsig, the SHS control signal is asserted low, causing switch 422 to open, thereby decoupling the capacitors 442 from node D.
Switches 434 and 435 are then simultaneously closed, which couples the gain stage 450 to capacitors 441, 442. The gain stage 450 produces an analog pixel signal Vpixel equal to the difference Vrst−Vsig. The analog pixel signal Vpixel is output on line 216.
FIG. 5, is a more detailed illustration of the load circuit 310. The load circuit 310 is comprised of transistors 311 and 312, coupled in series by their sources and drains, between node D and a source of ground potential. The gate of transistor 311 is coupled to the VLN_enable control signal, which is used to switch transistor 311 between an “on” and an “off” state. The gate of transistor 312 is coupled to the VLN_bias control signal to control the conductivity of transistor 312 to a predetermined level.
The pixel 100 (FIG. 1) is susceptible to a type of distortion known as eclipsing. Eclipsing refers to the distortion arising when a pixel outputs a pixel signal corresponding to a dark pixel even though bright light is incident upon the pixel. Eclipsing can occur when a pixel is exposed to bright light, as the light sensitive element 101 can produce a large quantity of photogenerated charge. Once the level of the incident light exceeds a certain threshold, the light sensitive element 101 becomes saturated and has generated a maximum amount of charge. An eclipse condition can occur if the light sensitive element 101 produces so much charge that during the time between the falling edge of the RST control signal and the falling edge of the SHR control signal (i.e., when the transfer transistor 111 is set to a non-conducting state) at least some of the photo-generated charges spill over the transfer transistor 111 and make their way to the floating diffusion node C. This diminishes the reset voltage at the floating diffusion node and can cause the pixel 100 to output an incorrect (i.e., diminished voltage) reset signal Vrst. This, in turn, can cause the reset and photo signals Vrst, Vsig to be nearly the same voltage. For example, the photo and reset signals Vrst, Vsig may each be approximately 0 volts. The pixel output signal Vpixel which equals (Vrst−Vsig), can therefore become approximately 0 volts, which corresponds to an output voltage normally associated with a dark pixel.
An anti-eclipse circuit can be used to mitigate against the effect of eclipsing. Conventional anti-eclipse circuits detect the presence of an eclipse condition by monitoring the voltage level of the reset signal and determining if that voltage level is abnormally low. If so, the reset signal can be pulled up to the proper level by clamping the column output line to a voltage source. The proper voltage for the voltage source is the normal reset signal voltage level. Unfortunately, this voltage varies from imager to imager because the voltage is sensitive to semiconductor process variations. As a result, the voltage source is typically a controllable voltage source, such as a transistor having a source/drain coupled to a power supply voltage and a gate coupled to a control signal, typically designated as the AE_voltage bias signal. Post manufacturing calibration could be done to set the AE_voltage bias signal to a proper level to permit the anti-eclipse circuit to pull the reset signal to the proper voltage when an eclipse condition is determined. Accordingly, there is a need and desire for an anti-eclipse circuit, which is not dependent upon monitoring the voltage level of the reset signal, and which can operate without requiring calibration.